BinaryRoot

With over 15 years of experience, I have cultivated a multifaceted professional journey that traverses the realms of Semiconductor Design Validation and System Software Development. At my current role in Intel, my tenure as a Senior IP Validation Engineer has been characterized by intricate involvement in the validation of critical IPs for Intel’s forthcoming silicon innovations. My responsibilities primarily focused on validating High-Speed IO integral to the Xeon Server IP, adhering strictly to PCIe protocol specs to ensure compliance with Intel’s quality benchmarks.
Gathered and defined requirements and test specifications for validation plans and Python-based test cases, aligning them with FPGA and Simics simulations. Proactively improved product testability, extendibility, and re-use within the validation process, implementing methodological enhancements for more efficient RTL drop validation. My primary ownership over the validation of IP Cache Coherency standards and Coherency protocols underscores my commitment to certifying seamless interoperability and functionality at the pre-silicon stage. In my preceding role at UST Global, as the Tech Lead and Senior Developer, I navigated the intricate world of technical project coordination.
My ability to orchestrate the efforts of a team and ensure the timely completion of projects, underscores my leadership and organizational skills. The development of the ‘System Mode and Redundancy’ module, aligning with the EN50128 safety standard, demonstrates my mastery over intricate system transitions and redundancy protocols. My accomplishments include crafting modules adhering to functional safety standards, creating communication softwares, and implementing innovative test frameworks. My commitment to quality through design patterns, Agile practices, and industry standards highlights my well-rounded capabilities.
In encapsulation, my professional journey paints a picture of an individual who has consistently evolved and excelled in diverse technology domains. My impact spans from the intricacies of semiconductor validation to the nuances of System Software Development, with my contributions leaving an indelible imprint on the projects I’ve been a part of. My mastery over tools, methodologies, and standards reflects my adaptability, while my capacity to tackle intricate challenges with tenacity and innovation showcases my intrinsic potential. My journey is a testament to unwavering dedication to the technology, and my future endeavors are bound to further enrich the landscapes I choose to explore.

Kiran

Email: gkiranp@gmail.com
Phone: (on-request)
Location: Malaysia

Skills:

System Programming: (12+ years) Linux & Unix based
Silicon Validation: (4+ years) Pre Silicon, RTL Debug, FPGA
Software Architecture & Project Management: (5+ years) Architectural Patterns, Design Patterns, Performance Profiling and Optimization, Design FMEA, SOW, HLD, Architecture Design, Code Review, Requirement Analysis, Requirement Management
Programming Languages: C++11 (8+ years), C++03 (13+ years), C (13+ years), Python (8+ years), Qt (7+ years)
Functional Safety (FuSa) Standards: EN50128, IEC 61508, MISRA, Adaptive AUTOSAR
Silicon Architecture: PCIe 5.0/6.0, CXL 1.0, Intel Xeon Arch, x86 Arch, FPGA
Software Development: Agile, TDD, SDLC
Operating Systems: Linux, VxWorks, Windows
Build & Tools: Cmake, Makefile, GoogleCPPTest, Git, LDRA Testbed, JIRA
Soft Skills: Communication, Leadership, Adaptability, Problem Solving, Time Management, Teamwork, Patience, Critical Thinking

Education:

Visvesvaraya Technological University, Belgaum, Karnataka, India
Bachelor Of Engineering
[Electronics and Communication]
[June 2004 - July 2008]

Experience:

Intel (M) Sdn Bhd, Penang, Malaysia - IP Design Verification Engineer
NOVEMBER 2023 - PRESENT [ IP Design Verification Engineer ]
NOVEMBER 2021 - NOVEMBER 2023 [ SoC Design Engineer]
Role: Senior IP Verification Engineer | My responsibilities primarily focused on validating High-Speed IO (HIOP: Host IO Processor) integral to the Xeon6 Server IP, adhering strictly to PCIe 6.0 protocol specifications to ensure compliance with industry standards and Intel’s quality benchmarks. Gathered and defined requirements and test specifications for validation plans and Python-based test cases, aligning them with FPGA and Simics simulation requirements. Proactively improved product testability, extendibility, and re-use within the validation process, implementing methodological enhancements for more efficient RTL drop validation. Designed and implemented an efficient, clean, and easily testable validation framework in Python and C++ using object-oriented design patterns, ensuring robustness and maintainability of the framework. My expertise extends to validating IP’s Cache Coherency standards and Coherency protocols, conducting primary-level RTL debugging with Verdi-waveforms, and utilizing debugging logics across various Transactors (XTORs) and Bus Functional Models (BFMs). In addition to my core responsibilities, I’ve led the design and development of functional tests to measure hardened IP performance, covering bandwidth and latency. Adept at developing volume system test suites, I identify problem areas and test coverage gaps, contributing significantly to the enhancement of overall test coverage. As a proactive leader, I engage in knowledge-sharing sessions, contributing insights on protocols, coherency, and programming. Consistently recognized as an outstanding performer, I bring a wealth of expertise and dedication to every aspect of my role.
Tools and Technologies: Architectural Patterns, Design Patterns, Performance Profiling and Optimization, C++, Python-3, Git, FPGA, Simics, Verdi, Agile.

UST Global Sdn Bhd, Penang, Malaysia - Sr. Technical Analyst
APRIL 2019 - OCTOBER 2021 [ Senior Technical Analyst ]
APRIL 2017 - MARCH 2019 [ Technical Analyst ]
Role: Lead/Senior Developer | Responsible for coordinating with the team and making sure technical projects are completed and delivered in time. Also responsible for the design and developing C++ based embedded system safety-critical software in the Trainborne project. Developed EN50128 safety standard module ‘System Mode and Redundancy’ using C++, which handles different system modes of transitions, like normal, degraded, fail-safe modes, during runtime. Module also interacts with different components, like Health Monitor, Radio Comm etc, in-order to find health status and communication status, depending on which the module decides the operating mode. The module has a decision-making factor, which is programmed for a redundant system to take over if the running system breaks. Developed communication parser modules using C++, like Computer Aided Dispatch (CAD) parser, which interacts with external CAD system using Motorola DIMETRA radio network, for voice and data communication and also two communication protocol wrappers, TRCP Protocol Handler, TCI Protocol Handlers, which in underneath uses Motorola standard SBEP serial protocol to communicate with external interfaces like TETRA modem, TRCP hardware and for communication between two TCI devices. Developed Health Monitor module, using C++ and observer design pattern, which monitors voltage, current and temperature levels and provides subscribe and receive health status of the system for different module-level interaction. Designed and developed a module Test Framework using Python and pySerial library interface, to perform command based testing of different components in TCI, later, the same framework is utilized for Test Automation in CI/CD purpose.
Tools and Technologies: C++03, C++11, Python-3, VxWorks RTOS, Kontron hardware, LDRA, Design Patterns, Qt4, EN50128, MISRA, Adaptive AUTOSAR, Agile-Scrum

Siemens Technology, Pune, India - Associate Consultant
AUGUST 2014 - MARCH 2017
Role: Senior Development Engineer | New feature development, bug fixing and maintenance of “Airlink” - a WiFi based embedded system software for Train Communication. Handled implementation of WPA2-PSK security feature in TU and AP using IEEE standard WPA_Supplicant and Hostapd packages, which enhanced security in wireless connectivity. Compiling and upgrading existing Linux Kernel of Airlink software, which in-turn involves upgrading of supporting open-source packages in Linux From Scratch. I have introduced ebtables, a filtering tool for a Linux-based bridging firewall inorder to filter out unwanted network traffic, hence including another level of network security. I have fixed bugs related to Frequency to Channel conversion for custom licensed wireless bands in Linux Kernel; fixed bugs related to system logging, by implementing “Observer pattern” in C++; fixed bugs related to watchdog and cgroups in the running system.
Tools and Technologies: C, C++, Linux From Scratch, Design Patterns, WPA_Supplicant, Hostapd, Network Routing, iptables, ebtables, IPSec, Linux Kernel, Linux Wireless.

UST Global, Bengaluru, India - Sr. Product Dev Engineer
MARCH 2011 - JULY 2014
Role: Senior Programmer | Design and Development of Multi-platform (viz. Linux, Win, Mac and Android) Software tools, Libraries and Drivers using technologies C++ and Qt. Design and development of Thermal Analysis Tool, which is used to categorize thermal capabilities of mobile platforms across different OSes. Design and development of MSR Read Write tool, which is used to read-from or write-to Model-Specific registers for different Intel platforms. Designed and developed Linear Graph Package, which is a customization of graph modules completely designed in Qt (without OpenGL). It supports customization of graph properties and layout, adding and deleting any number of graphs to layout at runtime. Design and development of Frequency Display tool, which is used to display all processor frequency values, graphic frequency values and memory frequency values. Assisted in integration and debugging MeeGo OS for Tablets running Intel Atom based Processor and Linux Kernel.
Tools and Technologies: C, C++, Qt, Makefile, Code Collaborator, TeamCity, Perforce, followed Agile methodology.

ASL Advanced System, Bengaluru, India - Project Engineer
FEBRUARY 2010 - FEBRUARY 2011
Role: Software Developer | Design and Developing embedded software, embedded protocols and Device Driver in Linux, for vehicle tracking systems. Worked on IVTS (Intelligent Vehicle Tracking System), which has built-in GSM and GPS modules for communication with Control Station Server. I have led a fresh embedded team in designing a touch sensitive based GUI using Qt and C++. I have also assisted in Cross Compiling Linux Kernel for ARM9 architecture. I am involved in complete design and development for Wagon Tracking System (WTS) application logic, board bring-up and BSP drivers for embedded system units. Device has in-built GSM, GPS modules and in-house battery charged through a solar panel. It has an intelligence of power-shutdown, to hold GSM messages in non-coverage areas and self-monitoring of battery charge and overheating. I am involved in the FOG PASS 1010 project for developing the BSP driver for USB Host 2.0 and the FAT32 file system for mass storage device support on ARM7 cortex. Other responsibilities were writing maintainable and extensible code in a team environment; consulted regularly with customers on project status, proposals and technical issues; directed software design and development while remaining focused on requirements.
Tools and Technologies: C++, C, Qt, OOPS, ARM7, ARM9, Linux Kernel, USB 2.0.

Advay Solutions, Bengaluru, India - Software Engineer
OCTOBER 2008 - FEBRUARY 2010
Role: Embedded System Programmer | Started a career as embedded engineer, and wrote maintainable and extensible code in a team environment. Worked in design and development of embedded software for CAN 2.0A/B protocol implementation, RF Modules and Bluetooth module for wireless transmission and Reception of Digital Data. Involved in developing Electronic Billing Machine (EBM), a consumer product, which prints formatted electronic bills and helps to store bill information.
Tools and Technologies: C, C++

References:

Available upon request.